Date/Time: 04-03-2018 - Tuesday - 05:00 PM - 07:00 PM
Pavan Kumar Vudumula1 Siva Prasad Kotamraju1

1, Indian Institute of Information Technology Sricity, Tada, , India

Silicon Carbide (SiC) based insulated gate bipolar transistor is a promising candidate for use in high voltage power devices, due to faster switching and high voltage blocking capabilities. The type of dielectric layer used in SiC power devices plays an important role in how the device performs. While SiC based transistors are commercialized, the combination of Silicon dioxide (SiO2) and SiC interface had compatibility concerns, and cannot sustain higher electric fields. An alternative is to replace the conventionally used SiO2 with high-K dielectrics that can sustain high electric fields. This approach has been attempted earlier with Hafnium dioxide (HfO2) as the main gate dielectric and sandwiching SiO2 between of HfO2 and SiC. Earlier research work has shown initial reduction and then increase in forward voltage drop (Vf)/ON state resistance (RON) with respect to temperature. However, there is no complete analysis of the static characteristics using HfO2-SiO2 as dielectric stack at higher temperatures. The purpose of this work is to understand the influence of HfO2 on the capacitance and switching characteristics at higher temperatures. This work highlights the changes in electrical characteristics by varying lattice temperature from 300 K to 700 K. The structure of the device is modeled by using Sentaurus TCAD. Apart from usual drift-diffusion and recombination models, lombardi model has been used to take mobility degradation at the interface into consideration. Uniform trap distribution up to the conduction band and the exponential distribution closer to the conduction band edge is defined within the band gap of SiC in the dielectric interface. Breakdown voltage (BV), switching characteristics using a clamped inductive load and variation of miller capacitance with respect to temperature is analyzed along with static characteristics. The doping of p-well and thickness of dielectric has been designed to adjust threshold voltage(Vth) closer to 3.5 V. It is to be noted that Vth generally reduces with an increase in temperature. The Ic-Vg and Ic-Vccurves at different temperatures are simulated. As expected, the reduction in Vth and transconductance (gm) has been observed from the I-V curves with increase in temperature. It has been observed that the saturation of trapping occurs at a lower gate voltage with the increase in temperature. The carrier lifetime in the buffer region is calculated using doping and temperature dependent carrier lifetime model. The turn off characteristics and ON state energy (EON) / OFF state energy (EOFF) with respect to temperature are simulated. It has been observed that the temperature has more influence on EON compared to EOFF. The influence of external gate resistance (Rg) on the switching characteristics will be discussed in the full paper.

Meeting Program

5:00 PM–7:00 PM Apr 3, 2018 (America - Denver)

PCC North, 300 Level, Exhibit Hall C-E