Description
Date/Time: 04-03-2018 - Tuesday - 05:00 PM - 07:00 PM
Suleman Qazi1 2 Payam Habibimehr2 Katerina Raleva3 Trevor Thornton2 Dragica Vasileska2

1, University of Engineering and Technology, Lahore, Punjab, Pakistan
2, Arizona State University, Tempe, Arizona, United States
3, University Sts Cyril and Methodius, Skopje, , Macedonia (the former Yugoslav Republic of)

Silicon-on-Insulator (SOI) technology possesses many advantages over bulk silicon such as the reduction of parasitic capacitances, excellent subthreshold slope, elimination of latch up and resistance to radiation [1]. For these reasons, SOI is the preferred technology for high-speed, high-temperature, and low-power microelectronic devices. SOI MOSFET devices employ a buried insulating thin layer, usually made of SiO2 to electrically isolate devices from the bulk semiconductor. Due to the poor thermal conductance, the buried dielectric layer thermally insulates the MOSFET from the bulk [2]. Consequently, the heat generated in SOI MOSFETs causes a larger temperature rise than in bulk devices under similar conditions, and this self-heating effect results in reduced carrier mobility and a corresponding decrease in the transconductance and speed. The self-heating effect can have significant impact on the device reliability as well.
This paper is an attempt to understand the effects of heat generation in SOI technology using a multiscale simulation and modeling scheme developed at Arizona State University in collaboration with IMEC in Belgium [3]. This scheme allows for simulation of carrier self-heating in the device and the corresponding thermal transport at the interconnect level, both at the same time. Previous work has successfully simulated self-heating in bulk devices, but this work strives to model the self-heating in SOI devices.
This scheme involves two components: 1). A numerical device level simulator that uses the Monte Carlo (MC) method to solve the Boltzmann transport equation (BTE) which is coupled with a Poisson solver to evaluate the charge distribution, while a self- consistent, energy balance equation is solved for optical and acoustic phonons to account for the self-heating effects. 2). The device simulator is coupled to a Silvaco module which solves for thermal transport in circuit interconnects using the Fourier law. Hence this multi-scale thermal simulation and modeling scheme is capable of analyzing thermal effects in nanoscale integrated electronics.


[1] R. Chau, B. Doyle, M. Doczy, S. Datta, S. Hareland, B. Jin, J. Kavalieros, and M. Metz, “Silicon nano-transistors and breaking the 10 nm physical gate length barrier,” in Proc. Device Res. Conf., Jun. 2003, pp. 123–126.
[2] T. Numata and S. Takagi, “Device design for subthreshold slope and threshold voltage control in sub-100-nm fully depleted SOI MOSFETs,” IEEE Trans. Electron Devices, vol. 51, no. 12, pp. 2161–2167, Dec. 2004.
[3] S. S. Qazi, A.R. Shaik, R.L. Daugherty, A. Laturia, X. Guo, E. Bury, B. Kaczer, K. Raleva and D.Vasileska, “Multi-scale modeling of self-heating effects in silicon nanoscale devices”, proceedings of the 15th International Conference on Nanotechnology (IEEE NANO), Rome, Italy, pp. 1461 - 1464, 2015.

Meeting Program
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5:00 PM–7:00 PM Apr 3, 2018

PCC North, 300 Level, Exhibit Hall C-E