Description
Date/Time: 04-03-2018 - Tuesday - 05:00 PM - 07:00 PM
Chun-Yu Liao1 Min-Hung Lee1

1, National Taiwan Normal University, Taipei, , Taiwan

Ferroelectric Zr doped in HfO2 as gate stack has been intensively and extensively investigated to integrate with FETs due to following current CMOS architectures and feasibility ALD (atomic layer deposition) supercycle approach [1][2]. The bi-stable state feature of hysteresis loops by ferroelectric materials satisfies the demands of voltage amplification concept for negative capacitance (NC) [3][4] and storage signal purpose for memory [5].
The discussion about NC reliability with sub-2.3kbT/q SS and wake-up effect is demonstrated. The ferroelectric (FE) coercive voltage for dipole switching is effectively reduced to a practicable NC onset voltage (<1V) after wake-up. This is one of ferroelectric characteristics for complete dipole switching beyond coercive voltage [6]. In order to observe this phenomenon of NC-FETs, the 5nm FE-HZO FETs are performed double sweep with the range from small to large. In order to reach the FE/NC region, the applied voltage needs high enough for complete dipole switching, and coercive E-field approaches to 2MV/cm. A gradual transition of ferroelectricity with crystallization temperature increasing results in subthreshold swing (SS) < 60mV/dec and hysteresis loop formation. The device by gate-last is more stable than that of gate-first due to well Source/Drain activation. It is promising to use ultra-thin FE-HZO as the guidelines for NC and memory applications. To develop a practicable FE-coercive/NC-onset voltage is an important issue for evaluating this technology.
The authors are grateful for the funding support from the National Science Council (MOST 105-2628-E-003-002-MY3, 106-2221-E-003-029-MY3 & 106-2622-8-002-001), process supported by National Nano Device Laboratories (NDL) & Nano Facility Center (NFC), Taiwan.
Reference:
[1] M. H. Lee et al, IEEE J. of the Electron Device Society, vol. 3, no. 4, pp. 377-381, 2015.
[2] M. H. Lee et al, IEEE Electron Device Letter, vol. 36, no. 4, pp. 294-296, 2015.
[3] S. Salahuddin and S. Datta, NanoLetters, vol. 8, no. 2, pp. 405-410, 2008.
[4] S. Salahuddin and S. Datta, in IEDM Tech. Dig., 2008, pp. 693-696.
[5] J. Müller et al, in Symp. on VLSI Technology and Circuits, 2012, pp. 25-26.
[6] P. Sharma et al, in Symp. on VLSI Technology and Circuits, 2017, pp. T154-T155.

Meeting Program
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5:00 PM–7:00 PM Apr 3, 2018

PCC North, 300 Level, Exhibit Hall C-E