Ultra-shallow junctions have become more desirable in the semiconductor industry as devices have continued to shrink in size and non-planar devices such as FinFETs and 3D nanostructures have become more common. Semiconductor devices are traditionally doped using a combination of ion implantation or spin-on dopant and thermal diffusion techniques; however, these have limitations such as crystalline damage, use of hazardous chemicals, or glassy skin formation. Monolayer doping (MLD) is an attractive alternative for forming sub-50 nm junctions. A dopant-containing compound forms a conformal self-assembled monolayer on the surface, then is capped with an insulating oxide and activation via rapid thermal anneal to form an ultra-shallow junction. The monolayers are formed with a phosphorous-containing compound for n-type doping, and a boron-containing compound for p-type doping. Techniques such as SIMS and sheet resistance measurements are used to characterize junctions and doping profiles. P+N and N+P diodes are fabricated and characterized. An in-house process for fabricating MOSFETs utilizing MLD for source/drain doping is developed. Electrical data on sub-50 nm emitter diodes and MOSFETs will be presented.