In recent years, intensive studies have been carried out on field effect transistors (FETs) using vertical GaN or AlGaN/GaN nanowires1–3. Compared to the conventional two-dimensional (2D) GaN transistors with gate control on top of the 2D electron gas, such devices have better gate control around each nanowire and higher power outputs. However, such devices still suffer from the overheating problem of GaN devices, which can largely deteriorate the device performance. To better understand this critical issue, electrothermal studies are performed on vertical GaN transistors using a recently developed hybrid simulation technique4. For the transistor region, coupled electron and phonon Monte Carlo simulations are employed to track the movement and scattering of individual carriers and thus obtain accurate temperature predictions. Away from the transistor, the conventional Fourier’s law is used to obtain the temperature distribution across the sub-mm chip. Our results show that the device overheating can be largely affected by the large ballistic thermal resistance at the nanowire–substrate junction.
1. Jo, Y.-W. et al. First demonstration of GaN-based vertical nanowire FET with top-down approach. in 2015 73rd Annual Device Research Conference (DRC) 35–36 (IEEE, 2015). doi:10.1109/DRC.2015.7175539
2. Im, K.-S. et al. Fabrication of AlGaN/GaN Ω-shaped nanowire fin-shaped FETs by a top-down approach. Appl. Phys. Express 8, 66501 (2015).
3. Im, K.-S. et al. High-Performance GaN-Based Nanochannel FinFETs With/Without AlGaN/GaN Heterostructure. IEEE Trans. Electron Devices 60, 3012–3018 (2013).
4. Hao, Q et al. A hybrid simulation technique for electrothermal studies of two-dimensional GaN-on-SiC high electron mobility transistors. J. Appl. Phys. 121, 204501 (2017).