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Adrian Ionescu1 Ali Saeidi1

1, Ecole Polytechnique Fédérale de Lausanne (EPFL), Lausanne, , Switzerland

Today, in the era of the Internet of Things era, the demands on enhanced integrated functionalities and on energy efficiency are even more important as the system miniaturization. Despite the fact that new paradigms in computing consider possible future roles of neuromorphic and quantum computing, it appears that, at least for next decade, CMOS will continue to play a dominant role. One of the remaining challenges for transistors with nanometer dimensions is the voltage scaling, today saturated at value near 0.7V. Today’s CMOS is a multi-material, three dimensional technology, which exploits quantum effects in semiconductors. However, the voltage supply of most advanced CMOS technologies is saturated due to incompressible thermionic subthreshold slope of the MOSFET, having as limit 60mV/decade at room temperature. In recent years, tremendous research efforts have been dedicated to devising new types of so called subthermionic steep slope switches, where the principle of the MOSFET switch is replaced with physical mechanisms that can provide such steeper transition between OFF and ON state, such as band-to-band tunneling and impact ionization. The goal is to enable further supply voltage scaling down to 0.2-0.3V, where logic state distinguishability is still granted with an improvement of energy efficiency of about 100x. Another idea is to apply a radically new technology booster on MOSFET and extend his life, by amplifying the gate signal using a differential negative capacitance (NC) in the gate stack. This could be done in a similar way in which a differential negative resistor would amplify a small signal. The result is a transistor body factor smaller than unity, reflecting the differential surface potential amplification, possible because of ferroelectric materials that can provide such a negative capacitance in the transistor gate stack.
In this paper, we will review, discuss and provide some concrete examples of how to achieve such sub-unity m factors by the negative capacitance effect materials to boost both MOSFETs and tunnel FETs performance at sub-10nn channel dimensions. The paper will discuss theoretical and experimental matching and stabilization conditions for NC and quantitative performance improvement in NC-MOSFETs and NC-Tunnel FETs by using PZT and, most interesting, ferroelectricity in doped high-k capacitors. The role of mono-domains versus multi-domains in ferroelectrics showing negative capacitance will be clarified. Moreover, we will present investigations about the very important role of gate leakage current in order to exploit the NC effect.
Overall, the paper will demonstrate that a deep sub-unity body factor by negative capacitance effect of field effect transistors can be engineered and applied for both MOSFETs and Tunnel FETs and stands as one of the most universal performance booster at nanoscale.

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