Phillip Jahelka1 Wen-Hui Cheng1 Rebecca Glaudell1 Rebecca Saive1 Harry Atwater1

1, California Institute of Technology, Pasadena, California, United States

In order for tandem-on-silicon solar cells to have impact, the top cell partner must be scalably manufacturable. This places constraints on both the overall cost per Watt at the cell level, and the fraction of that cost related to capital equipment expense (capex), which must be minimized for large-scale production. III-V compound semiconductors are promising tandem partners for silicon because of their ideal bandgaps, high radiative efficiencies and mature development. However, all previously proposed III-V tandem cells utilize epitaxial growth to define the cell and the high capital equipment and supply costs of epitaxy currently preclude the economic viability of these cells. In order to leverage the mature development of III-V devices without incurring the capex penalty of epitaxial growth, we have developed epitaxy-free processes for synthesis of GaAs and InP solar cells to serve as a tandem partner to silicon where III-V nanowire arrays are etched using liquid-phase metal assisted chemical or plasma etching process, and mechanically exfoliated from a bulk III-V crystal, enabling many cells to be generated from a bulk crystal source material. Electron and hole selective contacts and passivation materials are then grown using low-temperature, non-epitaxial techniques.

Because low cost, epitaxy-free designs do not permit use of standard epitaxially-grown III-V heterojunctions and window layers, we first developed a coupled optoelectronic model to understand the design space of the proposed solar cell using nontraditional heterojunction carrier-selective contacts. Using this model, we determined the optimal design to be a radial junction and discovered the absolute necessity of wide-bandgap carrier selective contacts due to the high density of photogenerated carriers throughout the nanowire. An optimized GaAs nanowire solar cell using TiO2 and ZnTe heteropartners operating as a single junction is predicted to be 26.5% efficient with 1.04V Voc and 28mA/cm2 Jsc, and have a greater spectral efficiency than a typical silicon cell, recommending its use as a tandem partner.

We have also performed proof-of-principle experiments for each fabrication step of our epitaxy-free cell processes. Highlights to date for InP include developing a plasma etching recipe for defining InP nanowires and successful exfoliation and fabrication of complete nanowire cells from their substrates by embedding them in a polymer handle. In addition, a nanowire-on-wafer InP/TiO2 heterojunction cell exhibits a 70% increase in photocurrent over its planar counterpart.
For GaAs cells, we have developed a room temperature and ambient pressure metal-assisted wet chemical etch for defining the nanowires, and have also exfoliated them from host wafer in a polymer handle. In addition, we have constructed ‘mini-cells’ demonstrating the non-epitaxial carrier selective contacts. A planar GaAs/CuI junction has demonstrated an open circuit voltage of Voc = 750mV.