Johan Knutsson1 Martin Hjort1 James Webb1 Peter Kratzer2 Sebastian Lehmann1 Chris Palmstrom3 Kimberly Thelander1 Rainer Timm1 Anders Mikkelsen1

1, Lund University, Lund, , Sweden
2, University of Duisburg-Essen, Duisburg, , Germany
3, University of California, Santa Barbara, Santa Barbara, California, United States

The III-V nanowire (NW) technology platform has reached a level of advancement that allows atomic scale control of crystal structure and surface morphology as well as flexible device integration. Combining this with Scanning Tunneling Microscopy/Spectroscopy (STM/S) opens up for studies of the role of nanostructure crystal variations down to the atomic level as well as direct in operando imaging of semiconductor surfaces response to electrical operation. Importantly, novel use of device processing allows all of this to be accomplished with a standard STM.

We have previously demonstrated atomically resolved STM/S on a wide variety of III-V NWs and standard devices [1-5]. We now use these methods for studying atomic scale crystal phase changes and the impact on local electronic properties on both GaAs and InAs NWs as well as demonstrating full atomic resolution STM during device operation [6-8].

Firstly, we explore the surface diffusion and alloying of Sb into GaAs NWs with controlled axial stacking of Wurtzite (Wz) and Zincblende (Zb) crystal phases[6]. We find that Sb preferentially incorporates into the surface layer of the Zb segments rather than the Wz segments. Density functional theory calculations find that this is related to differences in the energy barrier of the Sb-for-As exchange reaction. This demonstrate a simple processing-free route to compositional control at the monolayer level using crystal phase engineering.

Secondly, using 5K STM/S we measure local density of states of Zb crystal segments in Wz InAs NWs down to the smallest possible atomic scale crystal lattice change[7]. We find that the Zb phase signatures are seen in both the conduction and valence bands as well as in the band positions down to the smallest Zb segment. We also find indications of confined state effects due to the difference in bandgap between Wz and Zb.

Thirdly, we demonstrate a novel device platform that allows STM/S with atomic scale resolution across a III-V NW device simultaneously with full electrical operation [8]. The platform presents a significant step forward as it allows STM everywhere on the device surface and high temperature processing in reactive gases of the device. We demonstrate the new method by measurements on both InAs and GaAs NW devices with variable biases across the nanowire of up to 4 V. On InAs NWs we observe a surprising removal of atomic defects and smoothing of the surface morphology. As we use standard fabrication and scanning instrumentation our concept is widely applicable.

[1] E. Hilner et al., Nano Lett., 8 (2008) 3978; M. Hjort et al., ACS Nano 6, 9679 (2012)
[2] M. Hjort et al., Nano Lett., 13, 4492 (2013)
[3] M. Hjort et al., ACS Nano, 8 (2014) 12346
[4] J. L. Webb, et al Nano Lett. 15 (2015) 4865
[5] O. Persson et al., Nano Lett. 15 (2015) 3684
[7] M. Hjort et al Nano Lett., 17 (2017) 3634
[8] J. V. Knutsson et al ACS Nano, 11 (2017) 10519
[9] J. L. Webb et al, Sci. Rep. 7 (2017) 12790