2, Politecnico di Milano, Milan, , Italy
All-solution processed organic field effect transistors (OFETs) have the possibility of revolutionizing low-cost electronics thanks to the potential large area production, compatibility with flexible substrates and easy implementation in emerging technologies. OFETs are the basic building blocks for any plastic logic circuits but they are still showing limited speed of operation, thus limiting their applications. Most of the efforts in the last years have been dedicated to increase the organic semiconductor mobility, since it is an essential feature to improve the speed of OFETs. However the intrinsic high performances of the materials could not be completely exploited in short-channel transistors though they are highly attractive because of their high-frequency operation.
The main problem is the large contact resistance (Rc) between the electrodes and channel region, that is significantly larger compared to the channel resistances (Rch) in short channel transistors with a channel length of few microns. For this reason, injection in short channel OFETs is a challenging issue and a wide number of doping techniques and surface modifications of contact metals have been investigated, achieving modestly small Rc. In addition, in bottom-contacts top-gate transistor ( BCTG ) the overlap between bottom electrodes and top gate induce a parasitic capacitance contribution to the depleted channel capacitance that limit the frequency operation of OFETs. To overcome these problems, the use of the split-gate architecture, adapted from inorganic MOSFETs, has been recently successfully applied to OFETs, obtaining operation frequency in the order of 10 MHz, achieved by adopting self-aligned photolithographic steps. Using this peculiar structure, Rc can be reduced and kept constant by the split-gate voltage and the parasitic capacitance contributes can be minimized by controlling the gate electrodes overlap.
Here we report a BCTG low-voltage all-printed split-gate OFETs architecture, able to achieve hundreds of kHz regime, lower than previous reported but obtain through high resolution ink-jet printing technique, with a completely mask-less procedure. Split-gates are printed over the perylene dielectric layer, aligned with bottom contact Source and Drain electrodes, while the main-gate is printed above a second dielectric layer, minimizing the overlap with below electrodes. We can thus control carriers injection by controlling the split-gate potential and drastically reduce parasitic capacitance minimizing the gate overlap.
While a further downscaling of the device will be required to achieve higher frequency, the facile and high scalable printing process could open the possibility for the realization of high speed organic circuits, considering that the split-gate architecture is effective for both p- and n-type OFETs.
 Uemura, Adv. Mater. 2014, 26