Elena Stucchi2 1 Giorgio Dell'Erba2 Paolo Colpani2 Mario Caironi2

2, Istituto Italiano di Tecnologia, Milano, , Italy
1, Politecnico di Milano, Milano, MI, Italy

Organic field-effect transistors (OFETs) are being extensively studied in order to fully exploit the advantages of organic electronics, with the aim of developing low cost, large area, flexible electronic systems. One of the main factors hampering the diffusion of these devices into the consumer market is the high operating voltage, in the order of tens of volts, which negatively affects their power consumption and long term operational stability. In order to obtain transistors operating at low voltage, it is necessary to increase the gate capacitance per unit area. Two main strategies can be adopted, increasing the dielectric constant of the dielectric material employed or reducing the thickness of the dielectric layer.
In this work, we focus on the exploitation of thin dielectric films for the development of low voltage, transparent, flexible OFETs. A top-gate bottom-contact (TG/BC) configuration has been adopted, with PEDOT:PSS source and drain electrodes ink-jet printed on a flexible polyethylene naphthalate (PEN) substrate. Poly[2,5-bis(7-decylnonadecyl)pyrrolo[3,4-c]pyrrole-1,4(2 H,5 H)-dione-(E)-1,2-di(2,2′-bithiophen-5-yl)ethene] (29-DPP-TVT) and poly([N,N’-bis(2-octyldodecyl)-naphthalene-1,4,5,8-bis(dicarboximide)-2,6-diyl]-alt-5,5’-(2,2’-bithiophene)) (P(NDI2OD-T2)) have been used as p- and n-type semiconductors, both patterned by ink-jet printing. As gate dielectric, a thin film of parylene C has been employed both alone and in multi-layered structures with common low-k dielectrics. In all cases, the overall thickness of the dielectric layer is around 100nm.
After properly optimizing the process, we were able to obtain OFETs being operated at voltages lower than 10V. Despite the reduced thickness of the dielectric layer, very low gate leakage current density and high break-down voltage have been achieved. An array of optimized devices has been fabricated, and the yield, uniformity and flexibility have been tested, together with the long-term stability of the transistors.
CMOS inverter logic gates with balanced output characteristics have been fabricated, thanks to proper tailoring of the transistors’ channel widths. Additionally, ring oscillators and flip-flops have been produced, thus demonstrating the applicability of our devices as starting point in order to develop more complex complementary integrated circuits.