Steve Stoffels1 Karen Geens1 Xiangdong Li1 Ming Zhao1 Enrico Zanoni2 Gaudenzio Meneghesso2 Matteo Meneghini2 Niels Posthuma1 Marleen Vanhove1 Stefaan Decoutere1

1, imec, Leuven, , Belgium
2, University of Padova, Padova, , Italy

MOCVD growth of GaN-on-Si is the current standard to achieve a cost effective technology for GaN power devices. There are however some challenges related to growing on these substrates, in particular when scaling up the wafer size to 200 mm. The growth is heteroepitaxial with a large lattice and coefficient of thermal expansion (CTE) mismatch between the handling substrate, Si(111), and the (Al)(Ga)N buffer. Due to this mismatch a good control of stress during growth is required, necessitating dedicated stress compensation strategies for the buffer and this will limit the ultimate thickness which can be achieved for the (Al)(Ga)N buffer. Recently, investigations have been on-going to explore next generation substrates by looking into alternative technologies or solutions for the substrates, e.g. by modifying the silicon base material, using SOI substrates or using a completely different carrier substrate which has a better matching of the thermal expansion coefficient. For this work we have compared different novel substrate concepts from the point of reliability and buffer quality. A reliability evaluation has been performed on both the epitaxially grown buffers, as well as on devices fabricated on the buffers. For the buffers, the breakdown, lifetime and buffer induced current collapse have been evaluated. Imec’s latest p-GaN device technology has been used to fabricate power devices and evaluate the impact of the choice of substrate technology on the device reliability. For the engineered Si substrates we have investigated substrates with either a modification in the doping level and type, leading to different substrate resistivities, or miscut angles. One of the findings is the occurrence of a plateau in the vertical leakage characteristics. This plateau is thought to occur from a depletion in the silicon substrate at low p-type doping levels. Device reliability evaluation in this regime have revealed that the occurrence of the plateau is also correlated to an increase in device dispersion and Vt,shift. This is believed to occur due the a reverse polarization of the buffer just after stress. This plateau and device degradation can be completely avoided if highly doped p+ substrates are used. SOI substrates on the other hand represent an interesting alternative as they can enable co-integration of high-side and low-side power switches on a single chip, moreover a stress partitioning is happening on these wafers which allows to grow alternative buffer topologies with benefit in total thickness. Reliability testing on buffers and devices revealed the ability to reach high breakdown voltages (>900V) a very low buffer induced 2DEG collapse (<5%) and similar device reliability compared to regular GaN-on-Si.