Wan Khai Loke1 Kian Hua Tan1 Kwang Hong Lee2 Satrio Wicaksono1 Soon Fatt Yoon1

1, Nanyang Technological University, Singapore, , Singapore
2, Low Energy Electronic System IRG, Singapore, , Singapore

Monolithic integration of highly mismatched semiconductor material has received much attention because it allows the integration of devices with different circuit design on a platform that require less power consumption and create new application. In particular, devices in the mid-infrared range show high potential application in thermal imaging and sensing of gas molecules[1]. However, silicon (Si) is not suitable for detection of electromagnetic wave with wavelength longer than 1.1 µm due to its indirect energy bandgap of 1.12 eV. Indium arsenide (InAs) semiconductor material is a potential candidate as it has a direct energy bandgap of 0.35 eV. The cutoff wavelength of absorption of InAs photodetector is up to 3.5 µm at 300K. Integration of mid-infrared photodetector and Si CMOS circuit can be achieved by first performing heteroepitaxy growth of InAs on Si followed by wafer bonding[2] of Si CMOS on top of the InAs layers. The heteroepitaxy growth of InAs p-i-n photodetector on Si has been demonstrated earlier[3] through a thick buffer scheme which consist of linearly graded InAlAs layer in between the InAs p-i-n layer and GaAs layer. The total thickness of the buffer layer is about 2.1 µm. In this work, we present a study of two thinner buffer layer schemes: (i) InAs/GaAs/Ge/Si, and (ii) InAs/GaAs/GaP/Si, which both uses cation exchange method to perform heteroepitaxy growth of InAs on Si substrate. Thinner buffer scheme could reduce the risk of film cracking due to large thermal expansion coefficient mismatch between Si and III-V and possibly smoother surface morphology. Scheme (ii) requires migration enhanced epitaxy (MEE) of GaAs on Ge to switch from non-polar to polar semiconductor, whereas in scheme (ii), the transition is done during the growth of GaP on Si. In scheme (i), the cation exchange was done at the InAs/GaAs interface, whereas in scheme (ii), the cation exchange was done twice; first at the GaP/GaAs interface followed by another exchange at InAs/GaAs interface. Identical InAs p-i-n photodetector structures were grown on both schemes. Standard photolithography technique and wet etch process were used to fabricate the mid-infrared photodetector. X-ray diffraction (XRD) and transmission electron microscopy (TEM) were used to examine the crystalline quality of the layers.

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[2] X.S. Nguyen, S. Yadav, K.H. Lee, D. Kohen, A. Kumar, I.M. Riko, K.E. Lee, S.J. Chua, X. Gong, and E.A. Fitzgerald, IEEE Trans. Semicond. Manuf. 30(4), 456-461 (2017).
[3] W.K. Loke, K.H. Tan, D. Li, S. Wicaksono, S. F. Yoon, IEEE Photon. Technol. Lett. 28(15), 1653-1656 (2016).