3, KLA-Tencor, Milpitas, California, United States
2, Lawrence Semiconductor Research Laboratory, Tempe, Arizona, United States
Pure boron layers deposited on Si by chemical vapor deposition (CVD) from diborane are used in photodiodes for detecting low-penetration-depth beams such as EUV/VUV light and low-energy electrons down to 100 eV. These successful applications rely on a 700°C high temperature (HT) deposition to obtain smooth, uniform layers as thin as 2 nm. When deposited directly on n-Si, these layers can form p+n diodes that combine nm-shallow junction depth with low dark current and high stability/robustness with respect to high-dose exposures and chemically harsh environments. In addition, the 700°C deposition is fully compatible with front-end CMOS technology. In future applications such as backside-illuminated (BSI) imagers and (single-photon) avalanche diodes, the integration of PureB would be considerably facilitated by going down to the 400°C - 500°C low temperature (LT) deposition range, thus making the deposition back-end CMOS compatible as well.
In this paper, the properties of LT PureB deposition are studied with the purpose of obtaining optimal performance for as thin as possible layers. In past research, the LT diode characteristics were found to be very similar to the well-established HT diodes, displaying ideally low dark currents, and high responsivity radiation stability. This is because the PureB junction properties are determined by the B-to-Si interface and not doping of the bulk Si. However, the very smooth coverage achieved at 700°C is not readily reproduced at LT because the adsorption rate of B on Si is much lower, as is the mobility along the Si surface. The B atoms preferably attach to other B atoms rather than the Si so vertical growth on already deposited B atoms is promoted. This gives a high probability that not all Si atoms will be connected to a B atom before overgrowth with a complete, but usually very rough layer of pure B. The roughness, several nm instead of angstrom as in the HT case, significantly reduces the chemical robustness of the PureB, preventing the application in harsh environments.
Several PureB deposition conditions were studied and as-deposited layers were evaluated using analysis techniques such as HRTEM, AFM, optical profiling, XPS, and ellipsometry, as well as electrical characterization of diode I-V behavior and sheet resistance along the B-to-Si interface. The integrity of the layer was tested using a TMAH Si-etchant that revealed any weak spots in the layers through which the Si could be attacked.
More chemically robust 6-nm-thick PureB layers with a 3-nm roughness with ideal electrical characteristics were achieved at a growth temperature of 450°C. Two main parameters proved to be important for this result. For the first the B deposition rate should be fast enough prevent oxygen contamination of the Si surface but slow enough to allow a good first coverage of the surface. Second, the Si wafer cleaning steps should not include procedures that roughen the surface or bring the Si dopant atoms to the surface.