Semiconductor device performance receives all the attention however, reliability of these high performance devices is equally important. Device design to improve performance can sometimes lead to unintended reliability issues. The design and structural complexities of finFET device have always posed manufacturing challenges which need to be overcome to preserve device performance and reliability. As design rule gets smaller and smaller, structures are being grown in increasingly tighter spaces. eSiGe is grown to provide stress/strain in channel region to improve device performance. The structure can grow to fill all its space in the PMOS and further overgrow into the NMOS region, creating eSiGe overgrowth defect. Depending on the size of the overgrowth and its location within the device structure, this defect can pose reliability risks. Effective and complete inline detection of eSiGe overgrowth on a wafer is difficult and this could heighten concerns over device quality and reliability. In this work, we look at inline detection of eSiGe overgrowth.