2, Stanford University, Stanford, California, United States
3, University of Massachusetts Amherst, Amherst, Massachusetts, United States
4, Sandia National Laboratories, Albuquerque, New Mexico, United States
A major barrier to realizing neuromorphic hardware has been the development of analog memory with a linear and symmetric programmability required for neural algorithms and the energy efficiency to compete with conventional hardware. On one hand, CMOS-based floating gate memory (FGM) such as NAND Flash has a large programming voltage (>8V) that limits array-level energy efficiency. On the other hand, memristors, i.e. phase change memory and filament-forming metal oxides, suffer from non-linear weight updates and device-to-device variability that limits neural network accuracy.
To address these shortcomings, we introduce FGM based on ion insertion electrodes called ionic floating-gate memory (IFG). Similar to CMOS-based FGM, IFG is programmed via voltage pulses to a control gate that act to modulate the conductance of a semiconducting channel. However, for IFG, conductance switching occurs as ions are reversibly exchanged between the floating gate and channel through the process of ion insertion/extraction. Here, the floating gate acts as a reservoir of ions that is separated from the channel by an electronically-insulating but ionically-conductive solid electrolyte. After insertion/extraction through the electrolyte, ions diffusive throughout the channel volume in order to modulate the bulk doping.
IFG can provide benefits over CMOS which relies on hot carrier injection or Fowler-Nordheim tunneling in order to trap charges in oxides. First, bulk ion-insertion, also known as psuedocapacitance, significantly increases the charge-density per analog level, which relaxes the strict requirements for retention and supports many more levels for nanoscaled devices. Second, pseudocapacitance can act to reduce the floating gate potential to <100 mV, increasing programming linearity and allowing for control gates with low voltage thresholds (<1V). Here, we demonstrate an IFG device consisting of a newly-developed diffusive memristor (acting as a control gate) coupled to a non-volatile redox transistor (acting as a floating gate and channel) . Our IFG devices can be tuned to >50 resistance levels with a linear and symmetric programming response that is suitable for neural algorithms. Neural network simulations of the device performance are found to reach ideal accuracy when classifying MNIST hand-written digits.
 van de Burgt, Y. et al. Nature Materials 16, 414–418 (2017)