EP01.03.28 : Thermal TCAD Simulations of Silicon Dioxide Conduction Blocking Layers in GaN Vertical High Electron Mobility Transistors

5:00 PM–7:00 PM Apr 3, 2018 (America - Denver)

PCC North, 300 Level, Exhibit Hall C-E

Izak Baranowski1 Houqiang Fu1 Hong Chen1 Xuanqi Huang1 Jossue Montes1 Tsung-Han Yang1 Yuji Zhao1

1, Arizona State University, Tempe, Arizona, United States

Due to the increasing power demands, there is a need for more efficient, high power switching devices. GaN sees a lot of promise as a mean to meet this demand due to good on-resistance vs. breakdown voltage relationship. As a result, GaN-based electronic devices have seen a great deal of success in high power applications. The development of first generation GaN power devices has focused on lateral architectures, such as high-electron mobility transistors (HEMTs), fabricated in thin GaN layers grown on foreign substrates (e.g., sapphire, SiC, and Si). HEMTs achieve their high electron mobility with a lateral heterostructure
Despite the successful demonstration of GaN HEMTs in various power applications, these lateral devices have several drawbacks which significantly limit their performance especially for high power and high voltage applications (e.g., > 1,200V). These lateral devices suffer from several major degradation mechanisms including current-collapse, dynamic on-resistance, and an inability to support avalanche breakdown performance. Furthermore, at higher operation powers, lateral HEMTs become less attractive, since the blocking voltage is held laterally, the device length must increase in order to increase the breakdown voltage.

Recently, bulk GaN substrates have become widely available, thus enabling a new generation of GaN power devices based on vertical architectures. These vertical GaN power transistors hold the blocking voltage vertically, which allows the devices to achieve very high breakdown voltages without increasing device area. As in a lateral device, a heterostructure is used to create 2DEG. However the electrons are drawn by the drain into the bulk. Because of this, current collapse is not as much a concern in these devices since most of the conduction path is not near the trap rich surface. Current blocking layers (CBLs) are employed to confine the current to an aperture directly beneath the gate. Typically, p-GaN is used for the CBL, however, growing the p-GaN layer via metal organic chemical vapor deposition (MOCVD) results in the Mg being passivated by H, and therefore the hypothetical >3eV blocking layer is not achieved.

Therefore, there is impetus to explore other materials for CBL applications, such as SiO2, however, previous work on SiO2 CBL’s neglected thermal considerations. This work simulated using Silvaco TCAD two GaN Vertical HEMT devices, one with a conventional p-GaN CBL and one with a SiO2 CBL under both isothermal and non-isothermal conditions. At VD = 20 V and VG = 0 V, the SiO2 devices saw more heating, possessing a hotspot of 396 K, compared to the 379 K hotspot of the p-GaN device. In spite of the increased heating, the on-resistance was still lower for the SiO2 CBL device (0.266 mΩ cm2) than that of the conventional p-GaN CBL device (0.331 mΩ cm2).