Satrio Wicaksono1 Kian Hua Tan1 Wan Khai Loke1 Shuh-Ying Lee1 Bowen Jia1 Chiew Yong Yeo1 Soon Fatt Yoon1 Xiao Gong2 Sachin Yadav2 Annie Kumar2 Kian Hui Goh2 Yuan Dong2 Gengchiau Liang2 Yee Chia Yeo2

1, Nanyang Technological University, Singapore, , Singapore
2, National University of Singapore, Singapore, , Singapore

The introduction of III-V materials onto a Si-platform has been of tremendous interest for a very long time. III-V compound semiconductors high electron mobility and direct bandgap properties have been deemed to be the solution to the scaling problems in Si CMOS (complementary metal oxide semiconductor) transistor, through the use of high mobility channel and light emitting devices for optical interconnects. The application of such technology, however, is hindered by numerous issues. The considerable lattice mismatch between Si and high mobility III-V materials (i.e., (In)GaAs, InAs, GaSb, and InSb) and the lack of processes that are amiable to Si manufacturing environment for surface passivation, gate stack dielectric, and metal contacts schemes are some of them. Furthermore, as the substrate cost difference between III-V wafers and Si wafers is significant, a way to reuse and recycle the III-V substrates or create new III-V-on-Si substrates is needed.

In this work, a variety of solutions to bridge the lattice constant gap and to realize III-V CMOS and III-V laser on Si-based substrates will be highlighted. A combination of high-temperature annealing, migration enhanced epitaxy and buffer engineering techniques was developed on a Si-based substrate to minimise anti-phase boundary and threading dislocation defects. Two different buffer engineering were explored, an approximately 800nm-thick graded InAlAs buffer for lattice constant = InP lattice constant and a thinner interfacial misfit (IMF) buffer for lattice constants ≥ 6.0Å. The graded buffer approach was deployed to demonstrate InGaAs nFET and InGaAs n-FET monolithically integrated with AlGaAs/GaAs multiple quantum well laser on GeOI (germanium on insulator) substrate. Furthermore, the IMF sub-120 nm buffer approach allows integration of highly mismatch materials on GeOI substrate without having to go through a thick graded buffer process. This buffer technique alleviates some of the fabrication process challenges caused by the significant step height difference which exists where the graded buffer was used and allows a common gate stack formation processes to be developed. The use of IMF buffer enables demonstration of novel III-V (InAs) n-FET and (GaSb) p-FET or InAs n-FET and Ge p-FET monolithically integrated on the same Si-based substrate with excellent ION performance. Some III-V (InAs and InSb) and Ge(Sn) photodetectors grown on Si-based substrate operating at the mid-IR range will also be presented. Lastly, GaAs/Si heterogeneous wafer bonding with a specific bond energy of 478 mJ/m2 was realized at an annealing temperature as low as 140°C following a plasma activation step. This can potentially be combined with epitaxial lift-off processes to create new III-V on insulator wafers. The work done in this report was supported by the Singapore National Research Foundation through a Competitive Research Program (Grant No: NRF-CRP6-2010-4).