Ferroelectric Field Effect Transistors (FE-FET) with a ferroelectric material as a gate dielectric are the potential candidates for the next generation non-volatile memory technology because of their low operating voltage, non-destructive read out. On the other hand, two dimensional (2D) layered semiconductor materials have received considerable research interest as channel materials for next generation electronics because of their unique properties. Among these materials, more emphasis is given to molybdenum disulfide (MoS2), a member of transition metal dichalcogenide family , in many fields such as FETs, memories, photodetectors etc., because of its excellent properties such as intrinsic bandgap (1.2 eV), high electron mobility (410 cm2/V.s), good thermal stability and due to the possibility of creating atomically thin semiconductor membranes for a variety of applications. Therefore, MoS2 based FE-FETs can be the potential candidates for future ferroelectric memories. However, very few reports are available on FE-FETs based on MoS2 and hence device aspects such as materials physics and interface properties need to be understood to realize viable technology .
In this work, we report on the fabrication and characterization of Lead Zirconium Titanate (PZT) back gated MoS2 FETs for ferroelectric memories. The initial step of this work is the optimization of PZT films for their structural, compositional, electrical and ferroelectric properties using pulsed laser deposition. PZT (PbZr0.52Ti0.48O3) films of good ferroelectric properties (C= 4 µF/cm2, Pr= 40 µC/cm2, Ec= 170 kV/cm) have been deposited on Pt coated Si substrates using KrF (λ= 248 nm) laser where Pt severed as back gate electrode. MoS2 flakes were directly exfoliated on PZT film using standard scotch tape method. Multilayer MoS2 flakes (~7-10 nm) have been identified using optical microscope and confirmed with Raman spectroscopy, photoluminescence (PL) and atomic microscope. PZT back gated MoS2 FETs have been fabricated using standard two step e-beam lithography process followed by 50 nm Ni deposition using e-beam evaporation and lift off.
MoS2 FET with PZT back gating shows typical n-type MoS2 FET characteristics and the memory window of the devices significantly increases with the increase in gate voltage sweep ranges. A memory window of ΔVM~3.2 V has been realized when the gate voltage sweeps from -5 to 5 V at a fixed drain voltage (Vd= 1 V). The devices exhibited reproducible hysteresis, nonvolatile memory behavior with high Ion/Ioff ~105.
. A. Kuc et al, Phys.Rev. B, 83, 24, 245213 (2011).
. X-W. Zhang et al, IEEE Electron Device Letters, 36, 8, 784-786 (2015)