An attractive approach to realizing enhancement-mode (E-mode) GaN-based lateral heterojunction power transistors is to recess the barrier layer under the gate electrode, and thus remove the inherent positive polarization charges to obtain positive threshold voltage VTH . To suppress the gate leakage, the barrier layer should be replaced by insulating gate dielectric, forming a fully recessed MIS-FET or partially recessed MIS-HEMT. High electron mobility in the gate-controlled channel is maintained in MIS-HEMT with a thin barrier layer. However, the manufacturing of MIS-HEMT faces challenge in VTH uniformity control due to difficulties in precisely controlling the recess etching depth. In addition, the buried-channel MIS-HEMT typically exhibits worse VTH thermal stability than the surface-channel MIS-FET  as a result of the floating dielectric/AlGaN interface. Thus, the E-mode fully recessed MIS-FET possesses practical benefits in terms of manufacturing capability and device stability.
Obtaining high-quality interface with low Dit is one of the most critical challenges in MIS-gate. According to a first-principles calculation study, the GaN surface states distribution can be modified by nitridation with the shallow trap (i.e. close to EC) density greatly reduced . Interface protection is another technique to prevent the GaN surface from degradation at high temperatures (~ 800 oC)  at which high-quality gate dielectric is deposited. The high temperature is necessary to obtain a densified dielectric film with reduced defect density. With these techniques, SiNx gate dielectric (with the benefits of large conduction band offset of ~2.3 eV with GaN and relatively high dielectric constant of 7) deposited at 780 oC by LPCVD (low pressure chemical vapor deposition) is successfully integrated with recessed-gate structure to obtain E-mode MIS-HEMT/FET with enhanced VTH stability and gate dielectric reliability.
Both MIS-FETs and MIS-HEMTs exhibit small hysteresis △VTH < 0.1 V and low subthreshold swing SS ~ 97 mV/dec, benefiting from the greatly improved interface quality. As fully-recessed gate can reduce the sensitivity of VTH on the recess depth, higher VTH uniformity is obtained in MIS-FET. The MIS-FET also has more positive VTH (~2.4 V) than MIS-HEMT (~0.4 V). RON of MIS-FET (~13 Ω●mm) is slightly larger than that of the MIS-HEMT (~10 Ω●mm) due to lower MIS-channel electron mobility. The MIS-FET has a much better VTH stability than the MIS-HEMT, benefiting from the limited movement of EF at dielectric/GaN interface. In addition to thermal stability, the VTH of MIS-FET also shows better stability in long time NBTI stress.
In summary, surface nitridation and interface protection play critical roles in enabling a high-quality dielectric/III-N interface with low Dit. The fully recessed MIS-FET possesses many advantages in larger recess-depth tolerance, more possitive VTH, and higher VTH stability.