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Hiroaki Arimura1 Daire Cott1 Roger Loo1 Kurt Wostyn1 Guillaume Boccardi1 Jacopo Franco1 Sonja Sioncke1 Qi Xie2 Fu Tang3 Xiaoqiang Jiang3 Michael Givens3 Eddie Chiu4 Jerome Mitard1 Dan Mocuta1 Nadine Collaert1

1, imec, Leuven, , Belgium
2, ASM Belgium, Leuven, , Belgium
3, ASM International, Phoenix, Arizona, United States
4, HPSP, Sunnyvale, California, United States

Among high mobility channel materials, germanium is a unique candidate which offers both high hole and electron mobilities required for future CMOS. Forming a high-quality MOS interface is mandatory to bring out the full potential of Ge, while maintaining sufficient gate stack reliability is also compulsory on real devices. Recent reliability studies on Ge gate stack pointed out that the BTI of GeO2-based gate stack is a serious concern, while the use of Si-passivation layer on Ge shows potential to satisfy the reliability requirements [1]. An epitaxial grown Si passivation layer enables the use of a similar high-k/SiO2 gate stack, which has been intensively studied on Si devices. The presence of an SiO2 interface layer also makes band engineering possible by forming an interface dipole at the high-k/SiO2 interface [2]. On Ge pFETs, high hole mobility and superior NBTI reliability has been successfully demonstrated using a Si passivation layer [3]. In contrast, it is more challenging to achieve low Dit [4] and superior gate stack reliability on Ge nFET [5], even with a Si passivation layer. This presentation describes a way to achieve low Dit (5x1010 cm-2eV-1 around mid-gap) and superior gate stack reliability (effective oxide trap density of low x108 cm-2 at Eox=3.5 MV/cm) by using a Si-cap layer. While thinning down the Si-cap layer to an optimum thickness reduces Dit and improves electron mobility, while it increases the effective oxide trap density and degrades reliability because of the quantization in Si-cap layer and/or increase in the amount of Ge in the SiO2 interface layer [6]. To improve the gate stack reliability, La- or Mg-induced interface dipole is formed at the HfO2/SiO2 interface by inserting a thin ALD cap layer [7]. The interface dipole energetically decouples the electron traps in the high-k and the channel electrons, resulting in smaller VTH or VFB shift. Insertion of ALD LaSiO or MgOx is found to also suppress intermixing between HfO2 and SiO2, resulting in a 2-3x Dit reduction. Significant further Dit reduction is demonstrated by performing high-pressure anneal (HPA) in H2, lowering the Dit level down to 5x1010 cm-2eV-1 (1/20x) around mid-gap. Additionally, this presentation will also discuss EOT scalability and VTH tunability on Si-passivated Ge nMOS gate stack.

[1] J. Franco et al., IEDM 2013, p. 397.
[2] Y. Yamamoto et al., JJAP 46, p. 7251 (2007).
[3] J. Mitard et al., VLSI 2014, p. 34.
[4] C. H. Lee et al., IEDM 2010, p. 416.
[5] H. Arimura et al., IEDM 2015, p. 588.
[6] P. Ren et al., VLSI 2016, p. 32.
[7] H. Arimura et al., IEDM 2016, p. 834.

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