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Patrick Polakowski1 Teresa Büttner1 Tarek Ali1 Stefan Riedel1 Thomas Kämpfe1 Björn Pätzold1 Konrad Seidel1 Johannes Müller1

1, Fraunhofer, Dresden, , Germany

The 2011 discovery of a ferroelectric phase in doped hafnium oxide [1] and hafnium zirconium oxide solid solution [2] re-established the competitiveness of ferroelectric memory technologies. Mainly driven by the outstanding scalability and CMOS-compatibility of this new ferroelectric material, classical concepts such as FRAM, FeFET and FTJ are reentering the race for leading edge embedded and stand-alone memory solutions [3-6]. Especially the FeFET concept with its simple one-transistor cell design, non-destructive and low power read operation appears to be the main beneficiary of this new development. Scalability to the 2X nm node [3] and highly yielding memory arrays in the Mbit range are currently being demonstrated for hafnium oxide based FeFETs [7]. Nevertheless, a fundamental material understanding is needed to identify the main parameters improving the ferroelectric performance of the hafnium oxide thin films.
In this contribution we give an overview of the main parameters and their impact on the ferroelectric behavior of hafnium oxide. The thickness dependence and the directly associated consequence for the doping concentration of the film will be reviewed. The impact of different thermal treatments will be also discussed in relation to CMOS process flows, illustrating how the thermal budget of subsequent processes in the entire process flow can distinctively change the ferroelectric film properties. Furthermore, specific treatment conditions will be shown, which are further enhancing the ferroelectric properties of hafnium oxide films.

[1] T. Böscke et al., Applied Physics Letters 99 (10), 102903-102903, 2011
[2] J. Müller et al., Applied Physics Letters 99 (11), 112901-112901, 2011
[3] J. Müller et al., Symposium on VLSI Technology (VLSIT), pp. 25-26, 2012
[4] P. Polakowski, IEEE 6th International Memory Workshop (IMW), pp. 1-4, 2014
[5] K. Florent et al., Symposium on VLSI Technology (VLSIT), pp. T158-T159, 2017
[6] S. Fujii et al., Symposium on VLSI Technology (VLSIT), 2016
[7] S. Dünkel et al., IEEE International Electron Devices Meeting (IEDM), accepted for publication, 2017

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